Verilog HDL——分频 计数

分频 计数

module traffic(Clk_50M, Rst, Clk30, Clk_1Hz);
input Clk_50M, Rst;
output Clk30,Clk_1Hz;//------------分频器------------------
reg Clk_1Hz;//分频器  50M分频
reg[31:0] Cnt_1Hz;//计数
always@(posedge Clk_50M or negedge Rst)
beginif(!Rst)//Rst为0时  进行复位 置初值beginCnt_1Hz <= 1;Clk_1Hz <= 1;endelsebeginif(Cnt_1Hz >= 2)//为了显示波形这里25000000临时改为2beginCnt_1Hz <= 1;//计数器置1Clk_1Hz <= ~Clk_1Hz;endelseCnt_1Hz <= Cnt_1Hz +1;//计数end
end//------------计数器------------------
reg[7:0] Cnt30;//计数器
reg Clk30;
always@(posedge Clk_1Hz or negedge Rst)
beginif(!Rst)beginCnt30 <= 0;Clk30 <= 1;endelsebeginif(Cnt30 >= 30)beginCnt30 <= 0;//计数到30清零Clk30 <= ~Clk30;endelseCnt30 <= Cnt30 + 1;end
endendmodule 

仿真波形：

交通信号灯

/*
交通灯：红灯30s后转为绿灯，绿灯30s后转为红灯
*/
module traffic(Clk_50M, Rst, 
LedR_H, LedG_H, 
LedR_V, LedG_V, 
Seg7_VH, Seg7_VL, led15);
parameter S1 = 1;//x向红灯亮，y向绿灯亮
parameter S2 = 0;//x向绿灯亮，y向红灯亮
input Clk_50M, Rst;
output LedR_H, LedG_H, LedR_V, LedG_V;
output[6:0] Seg7_VH, Seg7_VL;
output led15;
reg LedR_H, LedG_H, LedR_V, LedG_V;//------------分频器------------------
reg Clk_1Hz;//分频器  50M分频
reg[31:0] Cnt_1Hz;//计数
always@(posedge Clk_50M or negedge Rst)
beginif(!Rst)//Rst为0时  进行复位 置初值beginCnt_1Hz <= 1;Clk_1Hz <= 1;endelsebeginif(Cnt_1Hz >= 25000000)beginCnt_1Hz <= 1;//计数器置1Clk_1Hz <= ~Clk_1Hz;endelseCnt_1Hz <= Cnt_1Hz +1;//计数end
end//------------计数器------------------
reg[7:0] Cnt30;//计数器
always@(posedge Clk_1Hz or negedge Rst)
beginif(!Rst)beginCnt30 <= 0;endelsebeginif(Cnt30 >= 30)beginCnt30 <= 0;//计数到30清零endelseCnt30 <= Cnt30 + 1;end
end//------------BCD码转换------------------
/*
调用译码器实例
SEG7_LUT hex4(Seg7_VL, CntDis[3:0]);
SEG7_LUT hex5(Seg7_VH, CntDis[3:0]);
*/
reg[7:0] CntDis;
always@(posedge Clk_50M)//8位二进制数转换BCD码beginif(Cnt30>29)beginCntDis[7:4] <= 3;//十位CntDis[3:0] <= Cnt30 - 30;//个位endelse if(Cnt30 > 19)beginCntDis[7:4] <= 2;//十位CntDis[3:0] <= Cnt30 - 20;//个位endelse if(Cnt30 > 9)beginCntDis[7:4] <= 1;//十位CntDis[3:0] <= Cnt30 - 10;//个位endelseCntDis <= Cnt30;//0-9end//------------状态转换------------------
reg state;//状态转换
always@(posedge Clk_1Hz)
begincase(state)S1:if(Cnt30 >= 30) state <= S2;S2:if(Cnt30 >= 30) state <=S1;default:state <= S1;endcase
endalways@(posedge Clk_50M or negedge Rst)
beginif(!Rst)beginLedR_H <= 0;LedG_H <= 0;LedR_V <= 0;LedG_V <= 0;endelsebegincase(state)S1://横向红灯亮，纵向绿灯亮beginLedR_H <= 1;LedG_H <= 0;LedR_V <= 0;LedG_V <= 1;endS2://横向绿灯亮，纵向红灯亮beginLedR_H <= 0;LedG_H <= 1;LedR_V <= 1;LedG_V <= 0;enddefault:beginLedR_H <= 0;LedG_H <= 1;LedR_V <= 1;LedG_V <= 0;endendcaseend
endassign led15 = state;
endmodule